Computer chips can contain multiple computing cores, memories, or processors, and these elements can communicate with each other while the chip performs its intended functions. In some computer chips, individual computer core elements may contain caches to buffer data communication with memories, and when the memory is shared among the computing cores, the data held in each individual core cache can be maintained in a coherent manner with other core caches and with the shared memory.
This coherence among the cache cores can be maintained by connecting the communicating elements in a shared bus architecture in which the shared bus includes protocols for communicating any changes in the contents of one cache to the contents of any of the caches. However, the speed at which such a shared bus can operate to communicate information among the agents connected to the bus is generally limited due to electrical loading of the bus, and this limitation generally become more severe as more agents are added to the shared bus. As processor speeds become faster and the number of shared elements increases, limitations on the communication speed on the bus impose undesirable restrictions on the overall processing capability of the chip.